Reduced hardware linear interpolator

Details Reduced hardware linear interpolator Reduced hardware linear interpolator

1997-07-30

1999-07-13

Mai, Tan V.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

G06F 738

Patent

active

059220430

ABSTRACT:
A linear interpolator for determining a weighted average between first and second terms having first and second weights, respectively. The linear interpolator includes a first multiplier for multiplying the first term and an inverse of the second weight to produce a first set of partial products, a second multiplier for multiplying the second term and the second weight to produce a second set of partial products, a carry-save addition ("CSA") tree and an adder. The CSA tree and adder combine the first set of partial products, the second set of partial products, and the first term to produce the weighted average. In another embodiment, the linear interpolator includes a plurality of multiplexers (muxes), the number of muxes being equal to the bit width of the second weight. Each mux selects between the first and second term, depending on whether the corresponding bit of the weight is a zero or one, to produce a plurality of partial products. The partial products are then right aligned a predetermined number of times and added in an accumulator along with the first term, thereby producing the weighted average.

REFERENCES:
patent: 5148381 (1992-09-01), Sprague
patent: 5345541 (1994-09-01), Kelley et al.
patent: 5402533 (1995-03-01), Kelley et al.

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