Large multiplier for programmable logic device

Large-scale multiplication with addition operation method and sy

Latching electronic circuit for random number generation

Lattice structure for IIR and FIR filters with automatic...

Layout structure for barrel shifter with decode circuit

Leading bit prediction with in-parallel correction

Leading one prediction unit for normalizing close path subtracti

Leading Zero Anticipatory (LZA) algorithm and logic for high...

Leading zero/one anticipator for floating point

Leading zero/one anticipator having an integrated sign selector

Leading-zero anticipator having an independent sign bit...

Lempel- Ziv data compression technique utilizing a dictionary pr

Lempel-Ziv data compression technique utilizing a dictionary...

Limit-cycle oscillation suppression method, system, and...

Limit-cycle-absent allpass filter lattice structure

Linear function generator method with counter for implementation

Linear interpolation operator

Linear intrasummed multiple-bit feedback shift register

Linear phase FIR sinc filter with multiplexing

Linear summation multiplier array implementation for both...