Reduced gate count differentiator

Details Reduced gate count differentiator Reduced gate count differentiator

2000-02-22

2003-06-17

Ngo, Chuong Dinh (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06581082

ABSTRACT:

BACKGROUND OF THE INVENTION
A. Field of the Invention
The present invention relates to a discrete-signal differentiator component. More specifically, the present invention relates to a method and apparatus for reducing the number of gates within a discrete-signal differentiator component. A reduction in gates can reduce the power consumption of the differentiator component. The differentiator component can be used in sigma-delta modulation.
B. Problems in the Art
The use of a discrete-signal differentiator component within a multistage noise shaper (MASH) is known in the art. In addition, the use of a MASH structure in fractional-N frequency synthesizers is also known in the art. Fractional-N frequency synthesizers are disclosed in U.S. Pat. Nos. 4,609,881, and 5,038,117, the disclosures of which are hereby incorporated by reference in their entirety.
Fractional-N synthesizers are used to synthesize output signals. The frequency of the output signal is a rational multiple of a reference signal. Frequency divider circuits are implemented such that they only divide by an integer value. Therefore, fractional division is realized by changing the divisor integer value during consecutive division cycles. The non-integer division ratios are realized by dividing by N+1, for example, instead of dividing by N, on a proportional number of division cycles. For example, if the desired rational divisor is taken to be N.1, the divisor value would be N for nine division cycles and N+1 for the tenth division cycle. Thus, when averaged over ten cycles, the division factor equals N.1 and an output frequency of a voltage controlled oscillator (VCO) will be N.1 times the reference frequency.
Logic gates are generally utilized to implement specific functional components, such as adders and latches, within the differentiator component. The logic gates in turn are comprised of transistors. The transistors may be bipolar junction transistors (BJT), field-effect transistors (FET), gallium arsenide transistors (GaAs), or any other type of transistor. All of the transistors need power. The transistors, particularly BJTs used in emitter coupled logic (ECL) families, are relatively inefficient with respect to power usage. Therefore, there is a need in the art for a differentiator component which can be implemented with a reduced number of gates. Reducing the number of gates will reduce the number of transistors needed to implement these gates. Reduction in transistors would lead to a reduction in power requirements for the differentiator component. Also, a reduction in gates would reduce the amount of heat produced by the differentiator component. Additionally, a reduction of gates would reduce the risk of failure of the differentiator component. Such a differentiator component is disclosed by the present invention.
C. Features of the Invention
A primary feature of the present invention is a discrete-signal differentiator component which requires fewer logic gates to implement the same function as prior art differentiator components.
Another feature of the present invention is a discrete-signal differentiator component which requires less power than those found in the prior art.
Another feature of the present invention is a discrete-signal differentiator component which requires fewer transistors that are susceptible to failure.
Another feature of the present invention is a differentiator component which implements a polynomial expansion of a z-transform characterization of the differentiator component's output.
An optional feature of the present invention is a differentiator component that realizes coefficients through implicit multiplication.
A further feature of the present invention is a method of reducing gates in a differentiator component.
These, as well as other features of the present invention, will be apparent from the following detailed description and claims in conjunction with the accompanying drawings.
SUMMARY OF THE INVENTION
An n signal differentiator component, wherein n is greater than or equal to two, comprises latches and adders having inputs and outputs. The connection of the inputs and outputs is dependent on a polynomial expansion of a z-transform characterization of an output of the differentiator component.
A method of reducing gates in an n signal differentiator component comprises constructing a circuit to perform the differentiator function. The circuit is dependent upon a polynomial expansion of the z-transform characterization of the differentiator component's output.


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