Reduced computation digital filter

Details Reduced computation digital filter Reduced computation digital filter

2002-01-16

2003-04-08

Mai, Tan V. (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C341S061000

Reexamination Certificate

active

06546407

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates to audio sample-rate conversion systems, and more particularly relates to multistage sample-rate conversion filters.
BACKGROUND OF THE INVENTION
For both historical and technical reasons, there have existed a number of industrial standards on audio digital signal sample rates. The well known examples are the 44.1 kHz sample rate for consumer CD players and 48 kHz for professional digital audio. This, in turn, has given rise to sample-rate conversion (“SRC”) systems for converting a stream of digital data at one sample rate to a stream of digital data at a different sample rate. However, the cost of existing SRC systems is high. This imposes a severe constraint in designing more affordable digital audio products that apply to various source signals.
Early implementations of SRC systems were done in a hybrid digital/analog domain. They were relatively simple, since all that is needed is a digital-to-analog (D/A) converter followed by an analog-to-digital (A/D) converter. The D/A converter runs at the input sample rate while the A/D converter is controlled by the output sample rate. If the output sample rate is lower, an analog anti-aliasing filter is provided between them. These three components are expensive and consume a large amount of power, if designed for minimum signal degradation.
Performing sample-rate conversion (SRC) in the digital domain has been a research/development topic for more than a decade. The article by R. E. Crochiere and L. R. Rabiner, “Interpolation and decimation of digital signals-A tutorial review,”
Proc. IEEE,
vol. 69, pp. 300-331, March 1981, is an excellent reference for understanding fundamental insights from early research results in this art area. Real-time, all-digital SRC systems are becoming more and more significant because digital processing of signals, such as voice, audio and video, appears to be increasingly dominant over traditional analog methods thanks to higher signal quality, rich features and the continually lowering cost of digital signal processing.
FIG. 1
shows a typical, all-digital SRC system
10
consisting of three basic building blocks: an interpolator (expander)
12
, a high quality lowpass digital filter
14
, and a decimator
16
. The expander
12
takes an input stream of samples at one frequency, for example F
s
—
in
, and digitally produces a stream of digital samples at a higher rate that is an integer multiple, designated R in this example, of the input rate. Thus, the output of expander
12
is a stream of digital samples at a rate of F
s
—
out
=R F
s
—
in
. The decimator does the reverse. Thus, the decimator
16
takes an input stream of samples at one frequency, for example X=R F
s
—
in
, and digitally produces a stream of digital samples at a lower rate, divided by an integer division factor, designated S in this example, of the input rate. This is referred to as decimation, or, alternatively, downsampling. Thus, the output of decimator
16
is a stream of digital samples at a rate of X/S=F
s
—
out
=(R/S)F
s
—
in
.
The reason for performing expansion followed by decimation is that the input sample rate and the output sample rate may not be a simple integer multiple of one another. The ratio of the interpolation factor R over the decimation factor S is the SRC ratio R/S where both R and S are positive integers. For R>S the SRC system is said to be operated in an SRC-UP mode, whereas an SRC-DOWN mode means R<S.
R and S may be chosen to have large values in order to achieve higher quality SRC. However, when the values of R and S are high, very high order digital filters, usually finite impulse response (“FIR”) digital filters, are necessary. Thus, as S and R increase, a greatly increasing amount of coefficient memory is required. For example, at a sample rate of 48 kHz an equi-ripple prototype FIR filter with transition bandwidth of &Dgr;f=4 kHz, passband ripples=10
−3
and stopband errors=10
−5
, has an order of approximately 128. The order of lowpass filter
14
in
FIG. 1
is 128R for an interpolation filter (R is the interpolation factor up to over 1000).
It is actually quite difficult or even impossible as a practical matter to design an equi-ripple FIR filter with tens of thousands of orders. In fact, the major difficulty encountered in existing audio SRC system, implemented either in an application-specific integrated circuit (ASIC) or on a programmable digital signal processor (DSP) such as a Texas Instruments TMS320 series DSP chip, seems to be large memory size and high computational complexity. For example, an ASIC described in an article by R. Adams and T. Kwan, “A stereo asynchoronous digital sample-rate converter for digital audio,”IEEE
J. Solid
-
State Circuits
, vol. 29, pp. 481-488, April 1994, needs tens of kilobytes of memory to store just a fraction of the nearly 10 million filter coefficients used.
Moreover, filter coefficient interpolation, which is performed to generate thousands of sets of required polyphase filter coefficients in real time, expends significant computational power which is provided by a hardware multiplier plus an accumulator. A similarly difficult situation is also encountered when a programmable DSP chip is employed. For example, see the article by S. Park et al., “A novel structure for real-time digital sample-rate converters with finite precision error analysis,”
Proc. Int. Conf. on Acoust, Speech and Signal Processing
, pp. 3613-3616, Toronto, 1991. Several kilobytes of memory are employed in these SRC systems for filter coefficients alone, in addition to their computational complexities falling in the neighborhood of 10 MIPs for one channel of high quality audio.
Therefore, attempts have been made using window techniques, for example using a Kaiser window, to design extremely high-order FIR filters. By using an interpolation technique in calculating required coefficients in real-time, a single-stage SRC filter system, such as the system
10
shown in
FIG. 1
, has become closer to practical, and hardware implementation examples have been reported. Examples may be found, e.g., in U.S. Pat. Nos. 4,780,892, 4,564,918, 4,825,398 and 4,748,578. However, these implementations fall short of the desired efficiencies allowing their utilization in affordable digital audio products for consumers.
Other attempts at avoiding the use of high-order filters make use of special functions such as Lagrange polynomials or B-spline functions. See, for example, T. O. Ramstad, “Digital methods for conversion between arbitrary sampling frequencies,”
IEEE Trans. Acoust, Speech and Signal Processing
, vol. ASSP-32, pp. 577-591, Jun. 1984, for an article on the former, and S. Cucchi et al., “DSP implementation of arbitrary sampling frequency conversion for high quality sound application,”
Proc. Int. Conf. on Acoust, Speech and Signal Processing
, pp. 3609-3612, Toronto, 1991, for the latter. These methods, however, all have the drawback of requiring a very large number of computations.
It is known that multistage decimation or interpolation filters are generally more efficient than single-stage filters, in terms of computational complexity. It appears that the same conclusion also holds on memory requirements of multi-stage filters over single-stage versions. It would therefore be desirable to have a multi-stage scheme employing a far smaller memory than required in the prior art to store some of the SRC filter coefficients, and have an accompanying arrangement for efficiently calculating the rest of the filter coefficients, in real time.
Therefore, it is an object of this invention to provide an efficient multistage multi-rate filter. It is also an object of the present invention to provide a multistage SRC filter that is more efficient in both computational and memory requirements than prior art multistage SRC filter implementations. It is a further object of the present invention to provide a multistage SRC that represents a balance of resource considerations.
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