Reduced-width low-error multiplier

Details Reduced-width low-error multiplier Reduced-width low-error multiplier

2005-10-18

2005-10-18

Mai, Tan V. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S550000

Reexamination Certificate

active

06957244

ABSTRACT:
This invention discloses a reduced-width, low-error multiplier that can be used in Digital Signal Processing (DSP). Specifically, this invention relates to a reduced-width, low-error multiplier capable of processing digital signals of communication systems such as a timing recovery circuit, a carrier recovery circuit, and a FIR filter, etc. This invention derives a binary compensation vector to compensate for the error caused by the reduction of area without any hardware overhead, and implements the compensation structure of an Array and a Booth multiplier to reduce hardware complexity.

REFERENCES:
patent: 6161119 (2000-12-01), Gabriel et al.
patent: 6167419 (2000-12-01), Saishi et al.
patent: 6298368 (2001-10-01), Miller, Jr.
Jer Min Jou et al., “Design of Low-Error Fixed-Width Multiliers for DSP Applications”,IEEE Transactions On Circuits and Systems-II: Analog and Digital Signal Processing,vol. 46, No. 6, Jun. 1999; and.
Sunder S. Kidambi et al., “Area-Efficient Multipliers for Digital Signal Processing Applications”,IEEE Transactions On Circuits and Systems-II: Analog and Digital Signal Processing,vol. 43, No. 2, Feb. 1996.

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