Reduced-hardware soft error detection

Details Reduced-hardware soft error detection Reduced-hardware soft error detection

2006-04-25

2006-04-25

Malzahn, D. H. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S534000

Reexamination Certificate

active

07035891

ABSTRACT:
A method and system are provided for performing soft error detection for integer addition and subtraction operations without the use of redundant logic. For integer addition and subtraction, compensate logic produces a compensate value utilizing arithmetic logic unit (ALU) result and operands. The compensate value is validated by the validate logic against a predetermined value to determine whether a soft error has occurred. Such compensate logic and validate logic operate on the integer operands and on the result produced by the ALU without redundant carry-propagate hardware.

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Wilson, R., “At 90 nm, process issues push into design flows,” Silicon Engineering, Electronic Engineering Times, Jul. 15, 2002.

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