Redundancy-free circuits for zero counters

Details Redundancy-free circuits for zero counters Redundancy-free circuits for zero counters

2005-05-17

2008-12-02

Ngo, Chuong D (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

07461110

ABSTRACT:
A more efficient method of counting the number of zeros in a 4-bit value generates three output bits (q0, q1and q2) from four input bits (a0, a1, a2and a3) according to the logic equations q0=not(a1+a2+a3+a4), q1=not(a0+a1), q2=a1(not a0)+not(a0+a2). These output bits yield the number of non-significant (leading or trailing) zeros in the 4-bit value. The invention may be implemented in a 16-bit zero counter having four 4-bit decoders, but is applicable to any number of zero counters. The output bits from the four 4-bit decoders can be combined to yield a 5-bit count whose most significant bit is a one when all input bits from all four of the 4-bit blocks are zero. A multiplexer stage derives two outputs based on a portion of the decode bits. For wider counters, the output stage uses four AOI21 gates to merge additional decode bits from a next lower 16-bit zero counter.

REFERENCES:
patent: 5568410 (1996-10-01), Bechade
patent: 5798953 (1998-08-01), Lozano
patent: 5844826 (1998-12-01), Nguyen
patent: 6779008 (2004-08-01), Erle et al.
E. Hokenek et al., “Leading-zero anticipator (LZA) in the IBM RISC System/6000 Floating Point Execution Unit,” IBM J. Res. Develop. v. 34, No. 1, pp. 71-77 (Jan. 1990).

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