Reduced-latency floating-point pipeline using normalization shif

Details Reduced-latency floating-point pipeline using normalization shif Reduced-latency floating-point pipeline using normalization shif

1998-03-13

2000-01-25

An, Meng-Ai T.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

708508, 708205, 3401462, 712222, G06F 700

Patent

active

060187565

ABSTRACT:
If the exponents of a floating-point-processor addition pipeline's input operands are equal, a signal (INVERT) that determines whether the pipeline's sole full-width carry-propagate mantissa adder (34) will invert one of its inputs results from an inversion-determination circuit (FIG. 11) that determines whether the sole set bit in a decoded normalization-shift signal (NORM.sub.-- SHIFT) occupies the same position as a set bit in a signal (FRAC.sub.-- A.sub.-- GT.sub.-- B) representing what the possible normalization amounts will be if a first of the mantissas is greater than the other, second mantissa. Consequently, a bit-comparison operation (56) that employs no full-width carry-propagate addition can determine the amount of normalization shifting to be performed by bit shifters (30 and 32) disposed in respective processing trains that generate mantissa inputs to the mantissa adder (34).

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patent: 5884062 (1999-03-01), Wichman et al.
patent: 5901076 (1999-05-01), Lynch

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