Clocking architecture to compensate a delay introduced by a...
Computer system having memory device with adjustable data...
Computer system having memory device with adjustable data...
Computer system providing low skew clock signals to a...
Computer system providing low skew clock signals to a...
Computer systems having apparatus for generating a delayed...
Concurrent execution of machine context synchronization operatio
Configurable fast clock detection logic with programmable...
Configurage data setup/hold timing circuit with user...
Control circuit for self-compensating delay chain for...
Control of I.C.'s having different command protocols...
Control signal generation circuit and data transmission...
Controller arrangement for synchronizer data transfer...
Converter circuit for synchronizing bus control signals...
Coordination of multiple multi-speed devices
Count calibration for synchronous data transfer between...
Count calibration for synchronous data transfer between...
CPU core to bus speed ratio detection
Cyclemaster synchronization in a distributed bridge
Cyclemaster synchronization in a distributed bridge