Configurable fast clock detection logic with programmable...

Details Configurable fast clock detection logic with programmable... Configurable fast clock detection logic with programmable...

2001-02-01

2004-11-09

Butler, Dennis M. (Department: 2115)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C713S500000, C713S600000

Reexamination Certificate

active

06816979

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for implementing a clocking scheme for single port FIFO memories generally and, more particularly, to a method and/or architecture for implementing a configurable fast clock detection logic with programmable resolution.
BACKGROUND OF THE INVENTION
First-In First-Out (FIFO) memories are often used as buffers between devices operating at different speeds. For a single port storage element, when the speeds of the interfaces are different, data flow may be interrupted. It would be desirable to implement a FIFO that detects clock speeds and automatically resolves the clock speed issues.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a first logic circuit and a second logic circuit. The first logic circuit may comprise one or more counters and may be configured to synchronize a plurality of input clock signals. The second logic circuit may be configured to detect and present a faster clock signal of the synchronized clock signals.
The objects, features and advantages of the present invention include providing a method and/or architecture for a implementing a configurable fast clock detection logic with resolution that may (i) provide programmable resolution (e.g., the resolution may be increased or decreased by adjusting, for example, a maximum count value), (ii) be easy and convenient to apply to different devices that need different resolution, (iii) provide automatic detection and configuration of device blocks to a faster clock, (iv) allow the creation of FIFOs (or multi-port memories) using a single port memory, (v) provide a digital circuit that selects a faster clock from multiple asynchronous clocks, using synchronous design methodology, and/or (vi) provide a scheme that is useful in systems where asynchronous clocks are nearly equal.


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