Method for controlling timing in reduced programmable logic...

Method for determining if a delay required before proceeding...

Method for generating a skew schedule for a clock...

Method for receiver delay detection and latency minimization...

Method for reducing tuning etch in a clock-forwarded interface

Method for transferring data across different clock domains...

Method for transferring data across different clock domains...

Method of compensating for delay between clock signals

Method of integrated circuit design checking using...

Method of matching different signal propagation times...

Method of timing calibration using slower data rate pattern

Method of timing calibration using slower data rate pattern

Method of timing calibration using slower data rate pattern

Methods and systems to reduce data skew in FIFOs

Methods for generating a delayed clock signal

Methods of determining whether a network interface card...

Multi-bit deskewing of bus signals using a training pattern

Multi-component module fly-by output alignment arrangement...

Multi-link extensions and bundle skew management

Multi-link receiver and method for processing multiple data...