Methods and systems to reduce data skew in FIFOs

Details Methods and systems to reduce data skew in FIFOs Methods and systems to reduce data skew in FIFOs

2007-05-08

2007-05-08

Elamin, A. (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C713S400000, C713S500000, C713S501000, C713S502000, C713S503000, C713S600000, C713S601000

Reexamination Certificate

active

10912397

ABSTRACT:
The disclosed invention provides methods and systems for writing and reading data in systems using multiple FIFO buffer elements. For each buffer element, a determination is made of when the rising edge of the read clock occurs during the second half of the write clock cycle. Responsive to this determination, the data written into the FIFO buffer element is shifted in order to reduce skew.

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patent: 6891415 (2005-05-01), Mikhalev et al.
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patent: 7116599 (2006-10-01), Au et al.
patent: 7143275 (2006-11-01), Cepulis et al.

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