Interface circuit device for performing data sampling at...
Interface circuit for selectively latching between different...
Interface controller that controls the rate at which data is...
IO based embedded processor clock speed control
Key controlling system, key controlling apparatus,...
Latch-and-hold circuit that permits subcircuits of an integrated
Logic to enable/disable a clock generator in a secure way
Logical bus overlay for increasing the existing system bus...
Low latency comma detection and clock alignment
Low power memory controller that is adaptable to either...
Low power method of responsively initiating fast response to...
Low power reconfigurable systems and methods
Low-speed DLL employing a digital phase interpolator based...
Main-board without restriction on memory frequency and...
Method and apparatus for a self-timed and self-enabled distribut
Method and apparatus for altering timing relationships of...
Method and apparatus for an integrated circuit having...
Method and apparatus for arbitrary resolution interval timeouts
Method and apparatus for controlling a clock signal of a...
Method and apparatus for controlling a clock signal of a...