Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data...
Reexamination Certificate
2008-09-09
2008-09-09
Cao, Chun (Department: 2115)
Electrical computers and digital processing systems: support
Clock control of data processing system, component, or data...
C713S500000
Reexamination Certificate
active
09636115
ABSTRACT:
A method and apparatus for handling, maintaining, and controlling network synchronization information emanating from a plurality of line card circuits is described. The technique described may be applied to a redundant pair of line card circuits, where one line card circuit is active, while the other is inactive. Line card activity latches are managed by means of hardware logic that may be configured at the time of line card commissioning. The activity latches are coupled to a logic element. An incoming clock signal is applied to the logic element. If an activity latch indicates that a line card circuit is active, the logic element provides the incoming clock signal as an outgoing clock signal to a control card circuit. If the activity latch indicates that the line card circuit is inactive, the logic element blocks the incoming clock signal from being passed and provides a static output level as the outgoing clock signal to the control card circuit. The control card circuit is provided with circuitry to receive the outgoing clock signals from multiple line card circuits. The circuitry is sensitive to whether or not the line card circuits are configured for redundant operation. One or more of these clock signals are then selected and used for network synchronization.
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Driediger Steven G.
Grah Adrian
Gryba John S.
Rochon Michel
Alcatel Lucent
Cao Chun
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