Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data... – Inhibiting timing generator or component
Reexamination Certificate
1998-08-25
2001-10-16
Butler, Dennis M. (Department: 2182)
Electrical computers and digital processing systems: support
Clock control of data processing system, component, or data...
Inhibiting timing generator or component
C713S322000
Reexamination Certificate
active
06304979
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention generally relates to controlling a clock generator in an electronic system and more particularly to a method and system for disabling and enabling a clock generator in a synchronous electronic system.
DESCRIPTION OF THE RELATED ART
Digital electronic systems rely on a clock generator to provide a clock signal that is used to synchronize operations within the system. With the proliferation of battery powered electronic devices, it has become more important to design electronic systems having low power requirements. One technique for conserving battery power is to turn off the clock generator during intervals in which performance of the system will not be adversely affected.
Once a clock generator has been disabled from a synchronous system, the restarting or re-enabling of the clock generator is a critical operation. Because there are no clock signals being generated in the system, the clock restart or wake-up must be triggered by an asynchronous event. While it is possible to restart the clock generator with an asynchronous signal, the synchronous electronic system cannot be notified of the clock restart with the asynchronous signal. The logic of the synchronous electronic system cannot be notified of the start of the clock with an asynchronous signal because any asynchronous signals introduced to the synchronous system would likely cause setup and/or hold time violations in the flip-flops that are integrated into the system circuitry, causing the system to fail.
In an instance in which a clock signal is disabled within a particular subsystem, but is still active in a broader system, U.S. Pat. No. 5,428,765, entitled “Method and Apparatus for Disabling and Restarting Clocks,” to Moore discloses a method and apparatus that re-enables the subsystem clock a fixed period of time after an external asynchronous wake-up event occurs. Although Moore works well for its intended purpose, Moore applies to systems where the transmission of a clock signal to a subsystem is disabled/enabled while a broader system clock continues to run, as opposed to the situation where a system clock generator is completely disabled such that no clock signals are available throughout the system. In addition, since Moore discloses a system in which a system clock continues to run, there is no need to notify the main system that a particular subsystem has been awakened.
In view of the problems involved with restarting a system clock in a synchronous system where the clock has been temporarily disabled, what is needed is a method and apparatus that disable/enable a clock generator and that notify the broader synchronous system that the clock has been restarted.
SUMMARY OF THE INVENTION
A method and apparatus for controlling a clock generator involve enabling the clock generator in response to an asynchronous signal and notifying a related synchronous system of the clock enablement with a synchronous signal, such that no asynchronous signal is introduced into the synchronous system. In the preferred embodiment, the register bits in a shift register are set by a synchronous signal to a value that disables the clock generator, and then the register bits can be flipped by the asynchronous signal to a value that enables the clock generator. The same synchronous signal that is used to disable the clock generator is used to initiate a synchronous counter that is subsequently used to notify the synchronous system, with a second synchronous signal, that the clock generator has been enabled. The notification occurs when the counter reaches a pre-established value.
In the preferred embodiment, the logic for controlling the clock generator is connected to the synchronous system and includes a state machine, the shift register, the counter, and an asynchronous edge detector. The synchronous system is an electronic system, such as a microprocessor or an application-specific integrated circuit (ASIC), that operates primarily in a synchronous manner. In a preferred embodiment, the system is part of a larger electronic device, such as a handheld computer or a portable telephone. The state machine is a logic element that indicates one of a finite group of states based on particular inputs. Preferably, the state machine utilizes standard logic and flip-flop devices to indicate either a first state in which the clock generator is running or a second state in which the clock generator is not running. When the state machine transitions from the first state to the second state, the state machine generates a signal which plays a role in the process that causes the clock generator to be disabled. The clock generator is located within an asynchronous clock domain of the logic and consists primarily of a clock crystal, an oscillator, and a phase-locked loop. The clock crystal, the oscillator and the phase-locked loop are all conventional devices that are formed and operated in a conventional manner. The clock signals generated by the clock generator are distributed through a clock distribution system to other logic elements in the synchronous system. The asynchronous edge detector is a conventional device that may consist of a delay line and an AND gate and that detects the edge of an incoming asynchronous event to generate an asynchronous pulse that is sent to the shift register.
Implementation of the shift register and the counter represent the focus of the invention. The shift register is a binary shift register that is formed from a series of flip-flops. In the preferred embodiment, the shift register has three inputs and one output. The first input receives a signal from the state machine to clear all of the register bits of the shift register to a value that disables the clock generator. The second input of the shift register provides a set bit to the shift register at each clock cycle. The number of clock cycles required for the set bit to travel through the shift register is equivalent to the number of flip-flops in the shift register. The shift register has a third input that receives an asynchronous signal from an asynchronous source. The third input is connected to the asynchronous set or reset of the flip-flops that make up the shift register. The reception of the asynchronous signal flips all of the register bit values in the shift register to a value that enables the clock generator and since no clock is running, setup and hold time violations are avoided. The output of the shift register is connected to the clock generator and provides the signal that either disables the clock generator or enables the clock generator in response to the various input signals to the shift register.
The counter is a conventional device that synchronously changes its counter value at each clock cycle while the clock generator is enabled. In the preferred embodiment, the counter value is refreshed to a pre-established initial counter value each time a synchronous refresh signal is received from the state machine.
The first operation performed by the logic is the disabling of the clock generator upon detection of a particular condition at the synchronous system (e.g., a continued period of inactivity). The disabling of the clock generator is initiated by the synchronous system generating a “go to deepsleep” signal that indicates to the state machine that the clock generator should be disabled. In response to the go to deepsleep signal, the state machine changes from its first state to its second state. The transition of the state machine from the first state (or run state) to the second state (or deepsleep state) causes the state machine to output a “load” signal. The load signal is transmitted to the counter and to the shift register. In response to the load signal, the counter is refreshed to its pre-established initial value and the shift register is cleared such that the register bits reflect a value that disables the clock generator. As a result, the shift register generates a “deepsleep_n” signal that is transmitted to the clock generator and operates to disable or shutdown the clock generator,
Butler Dennis M.
Fish & Richardson P.C.
Infineon Technologies North America Corp.
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