Low latency comma detection and clock alignment

Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data...

Reexamination Certificate

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Details

C709S224000, C709S228000, C709S232000, C709S236000, C710S058000, C370S465000, C341S095000, C341S100000

Reexamination Certificate

active

10863374

ABSTRACT:
An Infiniband device can be provided. The device can comprise an input port having a serialiser/deserialiser. The serialiser/deserialiser can comprise: a data buffer for storing data from a received serial data stream and for outputting the stored data in parallel groups and a code detector for detecting a predetermined code pattern in the serial data stream and generating a code detection output in response thereto. The serialiser/deserialiser can also comprise a transition detector for detecting transitions in the serial data stream and reconstructing a serial data clock therefrom, and for generating a plurality of parallel data clocks from the serial data clock, each parallel data clock having a different phase. The data buffer can be responsive to the code detection output to adjust a parallel data group start position within the serial data stream and to cause a selection of one of the reduced frequency clocks having a phase corresponding to the adjusted parallel data group start position.

REFERENCES:
patent: 6201829 (2001-03-01), Schneider
patent: 6393082 (2002-05-01), Nakamura
patent: 6407682 (2002-06-01), Jones
patent: 2003/0161429 (2003-08-01), Chiang
patent: WO 02/089405 (2002-11-01), None
patent: WO 03/075477 (2003-09-01), None
XILINX: “Virtex-II Pro Platform FPGAs: Functional Description”, Product Specification, Dec. 10, 2003, pp. 1-5, XP-002348226.
PCT International Search Report for International Application No. PCT/US2005/016775, 4 pages.
Written Opinion of the International Search Authority for International Application No. PCT/US2005/016775, 5 pages.

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