Latch-and-hold circuit that permits subcircuits of an integrated
Logic to enable/disable a clock generator in a secure way
Logical bus overlay for increasing the existing system bus...
Low latency comma detection and clock alignment
Low power memory controller that is adaptable to either...
Low power method of responsively initiating fast response to...
Low power reconfigurable systems and methods
Low-speed DLL employing a digital phase interpolator based...