Latch-and-hold circuit that permits subcircuits of an integrated

Details Latch-and-hold circuit that permits subcircuits of an integrated Latch-and-hold circuit that permits subcircuits of an integrated

1997-12-17

2000-12-12

Butler, Dennis M.

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

713400, 713500, G06F 104

Patent

active

061611891

ABSTRACT:
An integrated circuit comprises a semiconductor substrate having integrated circuitry formed therein. According to the present invention, the integrated circuitry includes a plurality of subcircuits, including first and second subcircuits that concurrently operate at diverse first and second frequencies, respectively. According to one embodiment, the integrated circuit has a clock signal that alternates between an active state and an inactive state at a third frequency and is broadcast to all of the subcircuits. In this embodiment, at least one subcircuit among the plurality of subcircuits, for example, a processor, operates in response to the clock signal at the third frequency, which is higher than the first frequency. According to another embodiment, the subcircuits each communicate with at least one other subcircuit via a latch-to-latch interface.

REFERENCES:
patent: 5455931 (1995-10-01), Camporese et al.
patent: 5710910 (1998-01-01), Kehl et al.
patent: 5828868 (1998-10-01), Sager et al.
patent: 5884100 (1999-03-01), Normoyle et al.
patent: 5937167 (1999-08-01), Arimilli et al.

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