Shared register architecture for a dual-instruction-set CPU to f

Shared register storage mechanisms for multithreaded computer sy

Shared resource queue for simultaneous multithreading...

Shared resources in a chip multiprocessor

Shared resources in a chip multiprocessor

Sharing data in internal and memory representations with...

Sharing information to reduce redundancy in hybrid branch...

Sharing instruction predecode information in a multiprocessor sy

Shift and insert instruction for overwriting a subset of...

Shift prefix instruction decoder for modifying register...

Shift prefix instruction decoder for modifying register...

Shifter for alignment with bit formatter gating bits from...

Shifter for alignment with bit formatter gating bits from...

Side tables annotating an instruction stream

Sign generation bypass path to aligner for reducing signed...

Signal processing apparatus

Signal processing device and method for supplying a signal...

Signal processing resource for selective series processing...

Signal processing system with distributed uniform memory

Signal processor capable of executing microprograms with differe