Shared resources in a chip multiprocessor

Details Shared resources in a chip multiprocessor Shared resources in a chip multiprocessor

2008-04-04

2010-11-23

Kindred, Alford W (Department: 2181)

Electrical computers and digital processing systems: processing

Processing architecture

Distributed processing system

C712S028000

Reexamination Certificate

active

07840780

ABSTRACT:
In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).

REFERENCES:
patent: 6401174 (2002-06-01), Hagersten et al.
patent: 6665788 (2003-12-01), Hughes
patent: 6976155 (2005-12-01), Drysdale et al.
patent: 2002/0029358 (2002-03-01), Pawlowski et al.

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