Manifold array processor

Manipulation of data

Map unit having rapid misprediction recovery

Mapping circuitry and method comprising first and second...

Mapping destination logical register to physical register...

Marking in history table instructions slowable/delayable for...

Marking queue for simultaneous execution of instructions in...

Massively parallel computer including auxiliary vector...

Massively parallel decoding and execution of variable-length...

Massively parallel instruction predecoding

Massively parallel multiple-folded clustered processor mesh arra

Master-slave latch circuit for multithreaded processing

Master-slave latches and post increment/decrement operations

Master/slave multi-processor arrangement and method thereof

Master/slave processor memory inter accessability in an...

Matched instruction set processor systems and method,...

Matrix of processors with data stream instruction execution...

Matrix processing method of shared-memory scalar...

Maximal tile generation technique and associated methods for...

Maximized memory throughput using cooperative thread arrays