Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2011-01-11
2011-01-11
Kim, Kenneth S (Department: 2111)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C710S316000, C712S225000
Reexamination Certificate
active
07870365
ABSTRACT:
In some embodiments, control and data messages are transmitted non-contentiously over corresponding control and data channels of inter-processor links in a matrix of mesh-interconnected matrix processors. A data stream instruction executed by a user thread of an instruction processing pipeline of a matrix processor may initiate a data stream transfer by a hardware data switch of the matrix processor over multiple consecutive cycles over a data channel. While the data stream is being transferred, the corresponding control channel may transfer control messages non-contentiously with respect to the data stream. The control messages may be messages received from other matrix processors and/or control messages initiated by a kernel thread of the current matrix processor.
REFERENCES:
patent: 4580215 (1986-04-01), Morton
patent: 4803617 (1989-02-01), Berarducci
patent: 4868818 (1989-09-01), Madan
patent: 4922408 (1990-05-01), Davis
patent: 5168572 (1992-12-01), Perkins
patent: 5253308 (1993-10-01), Johnson
patent: 5276895 (1994-01-01), Grondalski
patent: 5495570 (1996-02-01), Heugel
patent: 5598408 (1997-01-01), Nickolls
patent: 5603046 (1997-02-01), Wiles
patent: 5682491 (1997-10-01), Pechanek
patent: 6002851 (1999-12-01), Basavaiah
patent: 6038584 (2000-03-01), Balmer
patent: 6047391 (2000-04-01), Younis
patent: 6115763 (2000-09-01), Douskey
patent: 6128720 (2000-10-01), Pechanek
patent: 6167502 (2000-12-01), Pechanek
patent: 6304568 (2001-10-01), Kim
patent: 6651157 (2003-11-01), Galles
patent: 6678801 (2004-01-01), Greim
patent: 6678840 (2004-01-01), Kessler
patent: 6681316 (2004-01-01), Clermidy
patent: 6691216 (2004-02-01), Kelly
patent: 6769008 (2004-07-01), Kumar
patent: 6816562 (2004-11-01), Atkinson et al.
patent: 6820174 (2004-11-01), Vanderwiel
patent: 6845412 (2005-01-01), Boike
patent: 6851009 (2005-02-01), Regula
patent: 6898657 (2005-05-01), Smith
patent: 7017158 (2006-03-01), Sasaki
patent: 7174467 (2007-02-01), Helms
patent: 7185226 (2007-02-01), Chen
patent: 7222262 (2007-05-01), Prasadh
patent: 7231543 (2007-06-01), Lee
patent: 7240160 (2007-07-01), Hetherington
patent: 7281055 (2007-10-01), Glasco
patent: 7415594 (2008-08-01), Doerr et al.
patent: 7424698 (2008-09-01), Honary et al.
patent: 2003/0056084 (2003-03-01), Holgate
patent: 2003/0191855 (2003-10-01), Lee
patent: 2004/0215929 (2004-10-01), Floyd
patent: 2006/0095724 (2006-05-01), Singh
patent: 2006/0212677 (2006-09-01), Fossum
patent: 2007/0143578 (2007-06-01), Horton
U.S. Appl. No. 12/168,837, filed Jul. 7, 2008, entitled “Matrix Processor Initialization Systems and Methods,” inventors Cismas et al.
U.S. Appl. No. 12/168,849, filed Jul. 7, 2008, entitled “Matrix Processor Proxy Systems and Methods,” inventors Cismas et al.
U.S. Appl. No. 12/168,853, filed Jul. 7, 2008, entitled “Matrix Processor Data Switch Routing Systems and Methods,” inventors Cismas et al.
U.S. Appl. No. 12/168,861, filed Jul. 7, 2008, entitled “Matrix Processor Data Streaming Systems and Methods,” inventors Cismas et al.
USPTO, Office Action mailed Jun. 22, 2010 for U.S. Appl. No. 12/168,861, filed Jul. 7, 2008.
Cismas Sorin C
Garbacea Ilie
Kim Kenneth S
Law Office of Andrei D Popovici, PC
Ovics
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