Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2005-06-14
2005-06-14
Treat, William M. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C708S520000
Reexamination Certificate
active
06907513
ABSTRACT:
In accordance with a parallel matrix processing method adopted in a shared-memory scalar computer, a matrix to be subjected to LU factorization is divided into a block D of the diagonal portion and blocks beneath the D diagonal block such as L1, L2and L3. Then, D+L1, D+L2and D+L3are assigned to 3 processors respectively for processing them in parallel. Next, a block U is updated by adopting an LU-factorization method and C1to C3are updated with L1to L3and U. By carrying out this processing on the inner side gradually decreasing in size as blocks, finally, a portion corresponding to the D diagonal block remains to be processed. By applying the LU factorization to this D portion, the LU factorization for the entire matrix can be completed.
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Communication from Japanese Patent Office dated Mar. 30, 2004.
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