Maximal tile generation technique and associated methods for...

Details Maximal tile generation technique and associated methods for... Maximal tile generation technique and associated methods for...

2005-05-31

2005-05-31

Pan, Daniel (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Specialized instruction processing in support of testing,...

C716S030000, C716S030000, C716S030000, C714S725000

Reexamination Certificate

active

06901506

ABSTRACT:
A non-maximal arrangement of component tiles is reconfigured into a maximal arrangement. For each identified active segment of a first span not having a matching active segment in a second span, a maximal component tile having a width generally equal to the width of the identified active segment of the first span and a height generally equal to the distance separating the first and second spans is generated. The first span is then modified by deleting the matching active segment of the first span while adding each unmatched active segment of the second span. Maximal space tiles are generated from inactive segments of the spans using a similar process. The process is then repeated for each unselected span which fails to match the modified first span.

REFERENCES:
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patent: 6071315 (2000-06-01), Ramamurthi et al.
patent: 6216257 (2001-04-01), Agrawal et al.
patent: 6324673 (2001-11-01), Luo et al.
patent: 6546529 (2003-04-01), Dansky et al.
patent: 6763512 (2004-07-01), Xing
Xing et al.; U.S. Appl. No. 10/109,116; filed Mar. 28, 2002, Pub # 20030188270.
Xing et al.; U.S. Appl. No. 10/119,173; filed Apr. 8, 2002, Patent # 6,763,512.

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