Dual microcode RAM address mode instruction execution using...
Dual ROM microprogrammable microcontroller and universal...
Dual-mode VLIW architecture providing a software-controlled...
Dual-target block register allocation
Duplicator interconnection methods and apparatus for...
Dyadic DSP instruction predecode signal selective...
Dyadic DSP instruction processor with main and sub-operation...
Dyadic DSP instructions for digital signal processors
Dyadic instruction processing instruction set architecture...
Dyadic operations instruction processor with configurable...
Dynamic allocation of a buffer across multiple clients in...
Dynamic allocation of resources in multiple microprocessor...
Dynamic classification of conditional branches in global...
Dynamic concurrent atomic execution
Dynamic configurable system of parallel modules comprising chain
Dynamic conversion between different instruction codes by recomb
Dynamic data dependence tracking and its application to...
Dynamic data prefetching based on program counter and...
Dynamic endian switching
Dynamic execution layer interface for replacing instructions...