Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
1999-05-19
2001-11-13
Kim, Kenneth S. (Department: 2783)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S024000, C712S032000, C712S200000, C712S229000, C712S245000
Reexamination Certificate
active
06317820
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The technical field of this invention is microprocessors and digital signal processors, particularly those employing very long instruction words (VLIW).
BACKGROUND OF THE INVENTION
This invention pertains to the field of VLIW (Very Long Instruction Word) microprocessors and digital signal processors (DSP). This type of processor is characterized by the capability to utilize a high degree of instruction level parallelism (ILP), if this is available in the current application. Software applications developed for these processors exhibit a varying degree of latent ILP. Instruction level parallelism is the degree to which instructions are independent of each other and can be performed in parallel rather than in series. Applications with low latent ILP cannot exploit the full capabilities of a VLIW processor at all times. It often happens that the performance over a period of execution having lower latent ILP could be improved if task-level parallelism (TLP) were available as an alternative. Task-level parallelism refers to the capability of the processor to perform more than one independent task or instruction thread simultaneously. Such independent tasks typically include at least dozens or hundreds of instructions directed to independent problems. This greater utilization of the VLIW processor comes from the fact that during a period of low latent ILP many of the functional units of the processor are idle and thus could be used to run code from another task (or thread).
VLIWs are highly effective for regular, loop-oriented tasks such as are typical of the performance-sensitive aspects of digital signal processing and other “number-crunching” applications. Many modern applications require that one processor serve a mixture of programming paradigms. For example, a real-time embedded DSP application mixes both DSP and control processing tasks. The latter tasks typically have little latent ILP. Multi-thread execution would better suit the application when it is not solely involved in time-critical DSP kernel inner loop execution.
This problem has been addressed in a number of ways. One example of the prior art is the VLIW approach to multithreading as shown in U.S. Pat. No. 5,574,939 entitled “MULTIPROCESSOR COUPLING SYSTEM WITH INTEGRATED COMPILE AND RUN TIME SCHEDULING FOR PARALLELISM” by Keckler et. al. Keckler et. al. shows a VLIW system that can execute multiple threads that have been intermixed at compile time into a single VLIW word. In this approach a number of different instruction streams, which would have needed separate program counters, are statically scheduled together and run as a single combined instruction stream under control of a single program counter.
For superscalar-processors (which can be considered a form of hardware assembled VLIW system) running multiple time interleaved code streams is proposed. First, fetch N instructions from stream A, then N instructions from B, or fetch from A until processing stalls then switch to B until processing stalls, etc. An example of this type of processor operation is shown in U.S. Pat. No. 3,771,138 entitled “APPARATUS AND METHOD FOR SERIALIZING INSTRUCTIONS FROM TWO INDEPENDENT INSTRUCTION STREAMS” by Celtruda, et. al. Celtruda, et. al. teaches a processor with dual instruction buffers that are executed from in a time multiplexed fashion. U.S. Pat. No. 4,320,453 entitled “DUAL SEQUENCER MICROPROCESSOR” by Roberts, et. al., also teaches multi-threading by time multiplexing a processor. The primary VLIW machine patent from Denelcor, the HEP patent U.S. Pat. No. 4,229,790 entitled “CONCURRENT TASK AND INSTRUCTION PROCESSOR AND METHOD” by Gilliland, et. al. is also based on time multiplexing.
In addition a VLIW processor is particularly ill suited to interrupts. Interrupt handlers exhibit little ILP and switching the processor state to interrupt a VLIW's execution is costly and slow. Further, interrupt routines normally run only for a very short time. Thus a VLIW processor typically wastes resources handling interrupts.
SUMMARY OF THE INVENTION
This invention is a very long instruction word data processor including plural data registers, plural functional units and plural program counters. The data processor may be selectively operable in either a first or second mode. In the first mode program instructions are executed by selected ones of the data registers and selected ones of the functional units, under the control of a predetermined program counter. In the second mode a first program counter controls execution of program instructions using a first group of data registers and a first group of functional units, and a second program counter controls execution of program instructions using a disjoint second group of data registers and a disjoint second group of functional units.
Preferably, the plural data registers consists of an A side half and a B side a disjoint half, and the plural function units consists of an A side half and a B side disjoint set half. The first program counter is associated with the A side data registers and the A side function units and the second program counter is associated with the B side data registers and the B side function units. In the second mode the data processor can processes two independent program instruction streams simultaneously. The data processors includes plural control registers, at least one control register having duplicated for the A side and the B side. In the first mode operation is controlled by the A side component of the duplicated control register. In the second mode the A side component of the duplicated control register controls A side operation and the B side component of the duplicated control register controls B side operation.
The data processor may be changed from the first mode to the second mode and from the second mode to the first mode via instructions or the state of a control register.
In the second mode the data processor responds to two instruction streams, each accessing only corresponding halves of the data registers and function units. Alternatively, the data processor may respond to a first instruction stream including instructions referencing any of the data registers and any of the function units executed employing the A side function units by alternatively dispatching (1) instructions referencing the A side data registers and the A side function units and (2) instructions referencing the B side data registers and the B side function units. The data processor may include a set of B′ side data registers equal in number of the number of B side data registers used by the first instruction stream. In this alternative the data processor responds to a second instruction stream including only instructions referencing half the data processors and half the function units executed employing the B side function units.
The data processor includes a program memory storing instructions. In the first mode the data processor fetches N bits of instructions from the program memory each cycle corresponding to the first program counter. In the second mode the data processor fetches N bits of instructions for alternate program counters on alternate cycles. Alternatively, in the second mode the data processor fetches N/2 bits of instructions corresponding to the first program counter, and fetches N/2 bits of instructions corresponding to the second program counter.
The data processor includes interrupt steering and masking control logic allowing instructions to control whether the first instruction stream or the second instruction stream receives interrupts.
REFERENCES:
patent: 3573852 (1971-04-01), Watson et al.
patent: 3728692 (1973-04-01), Fennel, Jr.
patent: 3771138 (1973-11-01), Celtruda et al.
patent: 4197579 (1980-04-01), Otis, Jr. et al.
patent: 4229790 (1980-10-01), Gilliland et al
patent: 4320453 (1982-03-01), Roberts et al.
patent: 4344129 (1982-08-01), Asada et al.
patent: 4821187 (1989-04-01), Ueda et al.
patent: 4939638 (1990-07-01), Stephenson et al.
patent: 5530889 (1996-06-01), Kametani
patent: 5539911 (1996
Bartley David H.
Shiell Jonathan H.
Brady III W. James
Kim Kenneth S.
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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