Configuring a portion of a pipeline accelerator to generate...

Configuring sets of processor cores for processing instructions

Constant reconstructing processor that execute an...

Context pipelines

Control architecture for a high-throughput multi-processor...

Control of information processing using one or more peripheral a

Control processor dynamically loading shadow instruction...

Control unit and data processing system

Controller for a processor having internal memory

Controlling memory access devices in a data driven...

Controlling VLIW instruction operations supply to functional...

Converting logical to real number to access shared...

Copied register files for data processors having many...

Coprocessor extension architecture built using a novel...

Coprocessor forwarding load and store instructions with...

Coprocessor interface having pending instructions queue and...

Coprocessor interface transferring multiple instructions...

Coprocessor load data queue for interfacing an out-of-order...

Coprocessor processing instruction with coprocessor ID to...

Coprocessor processing instructions in turn from multiple...