Coprocessor load data queue for interfacing an out-of-order...

Details Coprocessor load data queue for interfacing an out-of-order... Coprocessor load data queue for interfacing an out-of-order...

2006-09-06

2011-10-04

Huisman, David (Department: 2183)

Electrical computers and digital processing systems: processing

Processing architecture

Microprocessor or multichip or multimodule processor having...

C712S216000, C712S220000

Reexamination Certificate

active

08032734

ABSTRACT:
A coprocessor interface unit for interfacing a coprocessor to an out-of-order execution pipeline, and applications thereof. In an embodiment, the coprocessor interface unit includes an in-order instruction queue, a coprocessor load data queue, and a coprocessor store data queue. Instructions are written into the in-order instruction queue by an instruction dispatch unit. Instructions exit the in-order instruction queue and enter the coprocessor. In the coprocessor, the instructions operate on data read from the coprocessor load data queue. Data is written back, for example, to memory or a register file by inserting the data into the out-of-order execution pipeline, either directly or via the coprocessor store data queue, which writes back the data.

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