Electrical computers and digital processing systems: processing – Processing architecture – Long instruction word
Reexamination Certificate
1998-07-29
2001-02-27
Pan, Daniel H. (Department: 2171)
Electrical computers and digital processing systems: processing
Processing architecture
Long instruction word
C712S024000, C712S210000, C712S208000, C712S235000, C711S167000
Reexamination Certificate
active
06195740
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to microprocessors and in particular to a technique for making effective use of unused areas that are present within instructions and for preventing unnecessary increases in code size and the number of execution cycles.
2. Description of the Prior Art
In recent years, increases in processing capability and processing speed of appliances using embedded microprocessors have led to an increasing demand for microprocessors (hereinafter simply referred to as “processors”) that can execute programs with high code efficiency. This means that it is preferable for there to be no unused areas in the instructions which compose a program.
In particular, when using fixed length instructions, such as VLIW (Very Long Instruction Words), there are cases when it is necessary to insert redundant codes, such as no-operation codes (“nop” codes), into instructions. VLIW are composed of a plurality of operation fields, with each operation field specifying an operation which corresponds to one of a plurality of operation units provided within a processor. Due to interdependencies between operations, however, it is not always possible to process a plurality of operations using parallel processing.
One conventional method of avoiding the decreases in code efficiency that accompany the insertion of “nop” codes is the VLIW-type computer system disclosed by Japanese Laid-Open Patent Application H08-161169.
FIG. 1
shows the instruction format used in the above technique.
As shown in
FIG. 1
, when a “nop” code needs to be inserted into operation field #
2
, this technique inserts a constant that is to be used by a different operation in place of the “nop” code into operation field #
2
and inserts instruction validation information into one part of operation field #
1
to show that the constant has been inserted. When executing this instruction, a processor first refers to the instruction validation information and so determines that only a constant is present in operation field #
2
. The processor then uses this constant as the operand of an operation. In this way, the existence of redundant areas within instructions due to the insertion of “nop” codes can be avoided.
The above technique, however, has a drawback in that the size of the constants that can be inserted into the redundant areas is limited.
As one example, when it is necessary to insert a “nop” code into a 32-bit operation field, it is not possible to insert any part of a 64-bit constant. similarly, when there is an unused 8-bit area in a fixed 32-bit instruction, it is only possible to use the unused area when inserting a constant which is 8 bits long or shorter. In this case, it is not possible to insert an absolute address which is expressed using 32 bits.
While the above technique may be effective when there is a relatively large redundant area in an instruction, when instructions have a relatively short length, such as 32 bits, any redundant area in the instructions will naturally be short, preventing the insertion of constants into a large number of redundant areas when using the above technique. This constitutes a major problem.
SUMMARY OF THE INVENTION
In view of the stated problems, it is the object of the present invention to provide a processor that fills unused areas that cannot be filled by a conventional processor with pieces of an operand for an operation and uses an instruction which gives the remaining pieces of the operand and an operation code for the operation. With this processor, code size and the number of execution cycles are reduced in comparison with a processor which uses instructions including all pieces of an operand and an instruction for executing an operation using the operand.
The object of the present invention can be achieved by a processor for decoding and executing an instruction, the processor including: an instruction register for storing the instruction; a decoding unit for decoding the stored instruction; a constant storage unit including a storage region; a constant transfer unit which, in a first case when the decoding unit has decoded that the instruction includes a first constant that should be stored into the constant storage unit, transfers the first constant from the instruction register to the constant storage unit; and an execution unit which, in a second case when the decoding unit has decoded that the instruction includes an operation code showing an operation that should be executed and a piece of an operand to be used for the operation, executes the operation using an operand obtained by linking the piece of the operand and a constant stored in the constant storage unit.
With the stated construction, pieces of an operand to be used for an operation are stored in a constant storage unit beforehand. An operation can be executed using the operand obtained by linking the stored pieces of the operand and the remaining pieces of the operand directly indicated by an instruction. Therefore, an operand for an operation is divided between instructions.
Accordingly, even when an instruction includes a small unused area which is smaller than an operand for an operation, this small unused area can be filled with one piece of the operand.
Furthermore, a single instruction can directly indicate the remaining pieces of the operand at the same time as executing an operation using the pieces of the operand stored in the constant storage unit and the remaining pieces of the operand. Accordingly, with this processor, the number of instructions is reduced in comparison with a processor which uses instructions including all pieces of an operand and an instruction for executing an operation using the operand. This assists in the generation of programs with high code efficiency.
Here, the execution unit may include: a first read unit for reading the constant stored in the constant storage unit in the second case; a second read unit for reading the piece of the operand from the instruction register; a link unit for linking the read constant with the read piece of the operand to generate an operand and outputting the operand; and an operation unit for executing the operation using the output operand.
With the stated construction, the first read unit and the second read unit perform their read operations in parallel. Accordingly, all pieces of an operand do not need to be stored in the constant storage unit before the execution of an operation using the operand. As a result, the processing time can be shortened by the time necessary to store into the constant storage unit the pieces of the operand which can be directly indicated with the processor of the present invention.
Here, the link unit may shift the read constant by a number of bits in the read piece of the operand and place the read piece of the operand at a blank position obtained after the read constant is shifted, so that the read constant and the read piece of the operand are linked.
With the stated construction, pieces of an operand that have been stored in the constant storage unit are shifted by the number of bits in the remaining pieces of the operand directly indicated by an instruction. As a result, the digit position in the constant storage unit for storing pieces of an operand beforehand can be fixed, eliminating the need to manage the digit position.
Here, the constant transfer unit may store a valid state data indicating whether the constant storage unit stores a valid constant, where when the valid state data indicates that the constant storage unit does not store a valid constant in the first case, the constant transfer unit transfers the first constant from the instruction register to the constant storage unit so that the first constant becomes a valid constant, and when the valid state data indicates that the constant storage unit stores a valid constant in the first case, the constant transfer unit transfers the first constant from the instruction register to the constant storage unit without deleting the stored valid constant and links th
Heishi Taketo
Higaki Nobuo
Miyaji Shinya
Odani Kensuke
Takayama Shuichi
Chen Te Su
Matsushita Electric - Industrial Co., Ltd.
Pan Daniel H.
Price and Gess
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