Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2007-02-20
2007-02-20
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S228000
Reexamination Certificate
active
10057723
ABSTRACT:
A method of parallel hardware-based multithreaded processing is described. The method includes assigning tasks for packet processing to programming engines and establishing pipelines between programming stages, which correspond to the programming engines. The method also includes establishing contexts for the assigned tasks on the programming engines and using a software controlled cache such as a CAM to transfer data between next neighbor registers residing in the programming engines.
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Adiletta Matthew J.
Bernstein Debra
Rosenbluth Mark B.
Wilkinson, III Hugh M.
Wolrich Gilbert
Coleman Eric
Fish & Richardson P.C.
Intel Corporation
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