Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2003-10-09
2008-08-26
Meonske, Tonia L. (Department: 2181)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S002000, C712S034000
Reexamination Certificate
active
07418574
ABSTRACT:
A peer-vector machine includes a host processor and a hardwired pipeline accelerator. The host processor executes a program, and, in response to the program, generates host data, and the pipeline accelerator generates pipeline data from the host data. Alternatively, the pipeline accelerator generates the pipeline data, and the host processor generates the host data from the pipeline data. Because the peer-vector machine includes both a processor and a pipeline accelerator, it can often process data more efficiently than a machine that includes only processors or only accelerators. For example, one can design the peer-vector machine so that the host processor performs decision-making and non-mathematically intensive operations and the accelerator performs non-decision-making and mathematically intensive operations. By shifting the mathematically intensive operations to the accelerator, the peer-vector machine often can, for a given clock frequency, process data at a speed that surpasses the speed at which a processor-only machine can process the data.
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Cherasaro Troy
Hellenbach Scott
Jackson Larry
Jones Mark
Mathur Chandan
Graybeal Jackson Haley LLP
Lockheed Martin Corporation
Meonske Tonia L.
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