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Processor including replay queue to break livelocks

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
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Processor livelock recovery by gradual stalling of...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
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Processor pipeline cache miss apparatus and method for...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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Processor pipeline including replay

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
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Processor pipeline stall based on data register status

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
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Processor programably configurable to execute enhanced variable

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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Processor stalling

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Processor system and method providing data to selected...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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Processor to efficiently rename decoded condition codes and...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Processor with a replay system that includes a replay queue...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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Processor with dependence mechanism to predict whether a...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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Processor with improved history file mechanism for restoring...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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Processor with multiple execution pipelines using pipe stage sta

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Processor with pipeline conflict resolution using...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
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Processor with registers storing committed/speculative data...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
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Program instruction rearrangement methods in computer

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Programmable delayed dispatch in a multi-threaded pipeline

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
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Providing parallel operand functions using register file and...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
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