Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
Reexamination Certificate
2005-03-08
2005-03-08
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Commitment control or register bypass
C711S141000, C711S137000, C711S138000, C711S133000
Reexamination Certificate
active
06865665
ABSTRACT:
There is disclosed a data processor for stalling the instruction execution pipeline after a cache miss and re-loading the correct cache data into any bypass devices before restarting the pipeline. The data processor comprises: 1) an instruction execution pipeline comprising N processing stages, each of the N processing stages performing one of a plurality of execution steps associated with a pending instruction being executed by the instruction execution pipeline; 2) a data cache for storing data values used by the pending instruction; 3) a plurality of architectural registers for receiving the data values from the data cache; 4) bypass circuitry for transferring a first data value from the data cache directly to a functional unit in one of the N processing stages without first storing the first data value in a destination one of the plurality of architectural registers; and 5) a cache refill controller for detecting that a cache miss has occurred at a first address associated with the first data value, receiving a missed cache line from a main memory coupled to the data processor, and causing the first data value to be transferred from the missed cache line to the functional unit.
REFERENCES:
patent: 4777589 (1988-10-01), Boettner et al.
patent: 4851993 (1989-07-01), Chen et al.
patent: 5590368 (1996-12-01), Heeb et al.
patent: 5778210 (1998-07-01), Henstrom et al.
patent: 6012137 (2000-01-01), Bublil et al.
patent: WO 9932979 (1999-07-01), None
Hennessey, Computer Architecture a Quantative Approach, 1996, Morgan Kaufman Publishers, pp. 70-73 and 191-194.*
Bannon, Peter, et al.; “International Architecture of Alpha 21164 Microprocessor”; Digital Equipment Corporation; Published May 3, 1995; pp. 79-87.
Chan Eddie
Jorgenson Lisa K.
Meonske Tonia L.
Munck William A.
STMicroelectronics Inc.
LandOfFree
Processor pipeline cache miss apparatus and method for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Processor pipeline cache miss apparatus and method for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Processor pipeline cache miss apparatus and method for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3447566