Processor pipeline stall based on data register status

Details Processor pipeline stall based on data register status Processor pipeline stall based on data register status

2005-12-06

2005-12-06

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Reducing an impact of a stall or pipeline bubble

C712S217000

Reexamination Certificate

active

06973561

ABSTRACT:
A method of recovering from loading invalid data into a register within a pipelined processor. The method comprises the steps of (A) setting a register status for the register to an invalid state in response to loading invalid data into the register and (B) stalling the processor in response to an instruction requiring data buffered by the register and the register status being in the invalid state.

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