Programmable delayed dispatch in a multi-threaded pipeline

Details Programmable delayed dispatch in a multi-threaded pipeline Programmable delayed dispatch in a multi-threaded pipeline

2007-09-04

2007-09-04

Treat, William M. (Department: 2181)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Reducing an impact of a stall or pipeline bubble

C712S213000, C712S215000

Reexamination Certificate

active

11065646

ABSTRACT:
Detecting a stall condition associated with processor instructions within one or more threads and generating a no-dispatch condition. The stall condition can be detected by hardware and/or software before and/or during processor instruction execution. The no-dispatch condition can be associated with a number of processing cycles and an instruction from a particular thread. As a result of generating the no-dispatch condition, processor instructions from other threads may be dispatched into the execution slot of an available execution pipeline. After a period of time, the instruction associated with the stall can be fetched and executed.

REFERENCES:
patent: 5337415 (1994-08-01), DeLano et al.
Daniel C. McCrackin, “Practical Delay Enforced Multistream (DEMUS) Control of Deeply Pipelined Processors”, IEEE Transactions on Computers, vol. 44, iss. 3, Mar. 1995, pp. 458-462.

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