Burst-loading of instructions into processor cache by execution
Burst/pipelined edo memory device
Bus arbitration circuit responsive to latency of access...
Bus control system
Bus controller initiated write-through mechanism
Bus controller initiated write-through mechanism with...
Bus filter for memory address translation
Bus frame protocol
Bus interface buffer control in a microprocessor
Bus interface controller for determining access counts
Bus interface controller for serially-accessed variable-access-t
Bus interface selection by page table attributes
Bus optimization with read/write coherence including...
Bus protocol for a switchless distributed shared memory...
Bus protocol for locked cycle cache hit
Bus snooping for cache coherency for a bus without built-in...
Bus timing protocol for a data storage system
Bypass custom array and related method for implementing ROM...
Bypassing a nonpaged pool controller when accessing a remainder
Byte alignment circuitry