Bus protocol for locked cycle cache hit

Details Bus protocol for locked cycle cache hit Bus protocol for locked cycle cache hit

1995-12-15

1998-07-28

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

711113, 711144, 711145, 711155, 711152, G06F 1214

Patent

active

057874867

ABSTRACT:
An apparatus and method are provided for maintaining lock characteristics while providing selective access to a cache during lock cycles. To guarantee that only one master accesses memory at a time, locked cycles are always passed to the internal arbitration unit of the memory controller, even if they are cache hits. If the local bus is not granted or cannot be guaranteed that it will be granted the bus for the locked cycle, the cycle is cancelled.

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