Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1998-07-17
2000-10-31
Ellis, Richard L.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
712225, G06F 1208
Patent
active
061417327
ABSTRACT:
An apparatus and method for accelerating interpretive environments may burst-load selected blocks of instructions into a processor cache. In an illustrated example, an interpretive instruction set implementing a virtual machine is modified to include a jump instruction embedded in each interpretive instruction. Each of the jump instructions points to a successive interpreter instruction, and the last jump instruction is a return to the main program. The interpretive instructions are crafted to occupy a single cache line as a compiled, linked, and loaded image. Consequently, burst-loading is accomplished by pointing to the jump instruction within an initial interpretive instruction. The cache registers a miss when the processor attempts to load the jump instruction, and a MMU loads a main memory block containing the initial interpretive instruction into a cache line. The jump instruction is executed, which results in the MMU loading a successive interpreter instruction into a cache line. This process continues until the final interpretive instruction is loaded. The final jump returns control to the main program. In this manner, the entire interpretive instruction set is rapidly burst-loaded into the processor cache. The interpretive instruction set is preferably pinned or fenced within the cache, and the processor can thereafter execute instructions with low latency in an interpretive environment.
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Ellis Richard L.
Novell Inc.
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