Bus optimization with read/write coherence including...

Details Bus optimization with read/write coherence including... Bus optimization with read/write coherence including...

1999-04-29

2001-07-03

Verbrugge, Kevin (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

Reexamination Certificate

active

06256713

ABSTRACT:

FIELD OF THE INVENTION
The disclosed invention relates to optimizing bus utilization while maintaining read/write coherence. Bus optimization is achieved by prioritization of read transactions over write transactions, where as many reads as possible occur contiguously.
BACKGROUND
As technology in the computer industry advances, the speed at which information is processed and accessed is increased. Certain instructions only require internal action by the processor, the processor speed controls the speed of a computer system in these situations. However, other instructions initiated by the processor require external transactions which are paced by the speed at which peripheral devices interact with the processor. Thus, optimization can be obtained by processing the transactions prior to presenting the transaction on the bus interface which requires a peripheral device to process the transactions. However, a difficulty can occur with data coherence. If data to a particular location is continuously updated and read, then the transactions to and from this location must be processed in the order in which the processor generated the transactions. Thus, when dealing with cache memory, a write request to a specific location in cache memory must be completed prior to a later request to read from that same location in memory. And conversely, a read request to a specific location in cache memory must be completed prior to a later request to write to the same location in memory.
The prior art includes at least two schemes. One scheme allows for complete in-order processing of transactions. An in-order implementation requires that a processor's read or write transactions be performed in the order in which the processor requests each transaction. This process ensures read/write coherence, but does nothing to optimize the bus utilization.
Another prior art scheme allows for out of order processing of transactions such that the read and write transactions to the cache memory can be prioritized to optimize the bus utilization. If a read transaction collides with a resident write transaction, the read data is forwarded from the write queue entry. This allows a read transaction to be performed without dependence upon the completion of a write transaction. However, this requires an undesirable increase in hardware and complexity on the processor chip or chip set.
Any advancement in the ability to optimize bus utilization while maintaining read/write coherence would be beneficial. Therefore, it is an objective in this invention to provide an increased bus utilization while maintaining read/write coherence.
THE SUMMARY OF THE INVENTION
The present invention provides a method and apparatus for optimizing bus utilization while maintaining read and write coherence. More specifically, the invention provides bus utilization optimization by allowing an optimal prioritization mechanism when there is no collision pending. When a collision pending is determined, then the read and write transactions are processed according to age of the transactions allowing for data coherency.


REFERENCES:
patent: 5530933 (1996-06-01), Frink et al.
patent: 5822772 (1998-10-01), Chan et al.
patent: 5978886 (1999-11-01), Moncton et al.
patent: 6038646 (2000-03-01), Sproull
Messmer, Hans-Peter.The Indispensable P.C. Hardware Book: Your Hardware Questions Answered.(Second Edition) Addison-Wesley. New York, 1995, pp. 211-226.
Kozierok, Charles M. “Function and Operation of the System Cache,”P.C. Guide.http://www.pcguide.com/ref/mbsys/cache/func-c.html, Dec. 16, 1998 vers., pp. 1-8.
Kozierok, Charles M. “Layers of Cache,”P.C. Guide.http://www.pcguide.com/ref/mbsys/cache/layers-c.html, Dec. 16, 1998 vers., pp. 1-3.

Affiliated with

Also associated with

Rating

Bus optimization with read/write coherence including... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bus optimization with read/write coherence including..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bus optimization with read/write coherence including... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2446303