Bus timing protocol for a data storage system

Details Bus timing protocol for a data storage system Bus timing protocol for a data storage system

1996-08-23

1998-12-15

Bragdon, Reginald G.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395309, 395881, 711113, 711114, 711167, 711168, 711165, G06F 1316

Patent

active

058505288

ABSTRACT:
In an data storage system having a bank of disk drives an addressable memory has a buffer memory coupled to a bus, a random access memory coupled to the buffer memory, an internal clock, and a logic network. The logic network is coupled to the bus and configured to transfer data among the buffer memory, the random access memory, and the bus in response to clock signals produced by the internal clock and clock pulses provided on the bus. The addressable memory is included in an interface and further includes a master memory unit and a slave memory unit.

REFERENCES:
patent: 4691294 (1987-09-01), Humpleman
patent: 5392422 (1995-02-01), Hoel et al.
patent: 5590369 (1996-12-01), Burgess et al.

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