Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2001-10-15
2004-06-08
Sparks, Donald (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S170000, C710S023000, C710S052000, C710S310000
Reexamination Certificate
active
06748506
ABSTRACT:
TECHNICAL FIELD
This invention relates to a bus frame protocol for transmitting data to one or more devices over a time-division multiplexed (TDM) bus.
BACKGROUND
A TDM bus receives multiplexed data from several devices and passes the data to different ports on a receiving device. On the receiving device, multiple pins are required to accommodate data for each of the ports. For example, in conventional TDM buses, there are four sets of pins for transmitting data to a device and four sets of pins for receiving data from a device. Thus, as the number of ports increases on a device, the number of pins on a conventional TDM bus can increase dramatically.
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Echartea Jesus Palomino
Lopez Guillermo Lopez
Suzuki Shiro
Chace Christian P.
Fish & Richardson P.C.
Intel Corporation
Sparks Donald
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