Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2005-10-04
2005-10-04
Vital, Pierre M. (Department: 2188)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S147000
Reexamination Certificate
active
06952761
ABSTRACT:
A translation lookaside buffer36within a data processor serves to translate a virtual address VA to a physical address PA and return attribute values that are used to switch40, 42a data access request between different busses44, 46of the processor18, 20.
REFERENCES:
patent: 5423008 (1995-06-01), Young et al.
patent: 5963976 (1999-10-01), Ogawa et al.
patent: 6044446 (2000-03-01), Joy et al.
patent: 6253290 (2001-06-01), Nakamoto
patent: 0 113 612 (1984-07-01), None
patent: 6 274638 (1994-09-01), None
ARM Limited
Nixon & Vanderhye P.C.
Vital Pierre M.
LandOfFree
Bus interface selection by page table attributes does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Bus interface selection by page table attributes, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bus interface selection by page table attributes will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3437828