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Scheme to partition a large lookaside buffer into an L2...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Scope-based cache coherence

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Scratch pad memories

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Scratch pad memories

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Scratchpad RAM memory accessible in parallel to a primary cache

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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SCSI-to-IP cache storage device and method

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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SDRAM L3 cache using speculative loads with command aborts...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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SDRAM read prefetch from multiple master devices

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Second chance replacement mechanism for a highly associative...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Secondary cache write-through blocking mechanism

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Secondary level cache for storage area networks

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Secondary path for coherency controller to interconnection...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Sectored least-recently-used cache replacement

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Segmentation suspend mode for real-time interrupt support

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Segmented distributed memory module cache

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Segmenting cache to provide varying service levels

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Segmenting cache to provide varying service levels

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Selectable two-way, four-way double cache interleave scheme

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Selecting a cache for a request for information

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Selecting a command to send to memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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