Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2000-08-29
2003-11-04
Moazzami, Nasser (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S122000, C711S123000, C712S205000
Reexamination Certificate
active
06643736
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a processing system and more particularly to a processing system that includes a scratch pad for improved performance.
BACKGROUND OF THE INVENTION
Processor architectures are utilized for a variety of functions.
FIG. 1
is a simple block diagram of a conventional processing system
10
. The processing system
10
includes a core processor
12
which controls a system bus interface unit
18
. The core processor
12
also interacts with an instruction cache and a data cache. Typically, the core processor retrieves information from the data cache or the instructions for operation rather than obtaining data from system memory as is well known. Since the data cache and instruction cache are smaller in size, data can be accessed from them more readily if it is resident therein.
In this type of processing system, oftentimes small routines are provided which can further affect the performance of the system. Accordingly, the caches are placed therein to is allow faster access rather than having to access system memory. Although these caches are faster than system memory, they still are relatively slow if the routine needs to be accessed on a continual basis therefrom. For example, small routines may take up several cycles which can become a performance bottleneck in a processing system. So what is desired is a system which will allow one to more quickly access and obtain certain routines and therefore improve the overall performance of the system in the data cache without wasting memory space.
The system must be easy to implement utilizing existing technologies. The present invention addresses such a need.
SUMMARY OF THE INVENTION
A processing system is disclosed. The processing system includes at least one cache and at least one scratch pad memory. The system also includes a processor for accessing the at least one cache and at least one scratch pad memory. The at least one scratch pad memory is smaller in size than the at least one cache. The processor accesses the data in the at least one scratch pad memory before accessing the at least one cache to determine if the appropriate data is therein.
There are two important features of the present invention. The first feature is that an instruction can be utilized to fill a scratch pad memory with the appropriate data in an efficient manner. The second feature is that once the scratch pad has the appropriate data, it can be accessed more efficiently to retrieve this data within the cache and memory space not needed for this data. This has a particular advantage for frequently used routines, such as a mathematical algorithm to minimize the amount of space utilized in the cache for such routines. Accordingly, the complexity of the cache is not required using the scratch pad memory as well as space within the cache is not utilized.
REFERENCES:
patent: 4843542 (1989-06-01), Dashiell et al.
patent: 5067078 (1991-11-01), Talgam et al.
patent: 5553276 (1996-09-01), Dean
patent: 5893159 (1999-04-01), Schneider
patent: 5922066 (1999-07-01), Cho et al.
patent: 5966734 (1999-10-01), Mohamed et al.
Arm Limited
Moazzami Nasser
Nixon & Vanderhye P.C.
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