Shadow register to enhance lock acquisition

Share masks and alias for directory coherency

Shared buffer having hardware-controlled buffer regions

Shared cache eviction

Shared cache for data integrity operations

Shared cache memory replacement control method and apparatus

Shared cache parsing and pre-fetch

Shared cache parsing and pre-fetch

Shared cache structure for temporal and non-temporal...

Shared cache structure for temporal and non-temporal...

Shared cache with client-specific replacement policy

Shared cache wordline decoder for redundant and regular...

Shared closure eviction implementation

Shared instruction cache for multiple processors

Shared instruction cache for multiple processors

Shared instruction cache for multiple processors

Shared intervention protocol for SMP bus using caches, snooping,

Shared memory multiprocessing system employing mixed...

Sharing monitored cache lines across multiple cores

Signal processor, prefetch instruction method and prefetch...