Sharing monitored cache lines across multiple cores

Details Sharing monitored cache lines across multiple cores Sharing monitored cache lines across multiple cores

2007-08-14

2007-08-14

Portka, Gary (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

Reexamination Certificate

active

10956685

ABSTRACT:
In one embodiment, a system comprises a first processor core and a second processor core. The first processor core is configured to communicate an address range indication identifying an address range that the first processor core is monitoring for an update. The first processor core is configured to communicate the address range indication responsive to executing a first instruction defined to cause the first processor core to monitor the address range. Coupled to receive the address range indication, the second processor core is configured, responsive to executing a store operation that updates at least one byte in the address range, to signal the first processing core. Coupled to receive the signal from the second processor core, the first processor core is configured to exit a first state in which the first processor core is awaiting the update in the address range responsive to the signal.

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Intel, “Prescott New Instructions Software Developer's Guide,” Jan. 2004, 92 pages.
International Search Report in Application No. PCT/US2005/033819 Mailed Dec. 29, 2006.

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