Shared intervention protocol for SMP bus using caches, snooping,

Details Shared intervention protocol for SMP bus using caches, snooping, Shared intervention protocol for SMP bus using caches, snooping,

1997-04-14

1999-08-31

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711173, 711146, 711143, 711108, G06F 1200

Patent

active

059467096

ABSTRACT:
A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. After a value (data or instruction) is loaded from system memory into a plurality of caches, one cache is identified as a specific cache which contains an unmodified copy of the value that was most recently read, and that cache is marked as containing the most recently read copy, while the remaining caches are marked as containing shared, unmodified copies of the value. When a requesting processing unit issues a message indicating that it desires to read the value, the specific cache transmits a response indicating that it cache can source the value. The response is transmitted in response to the cache snooping the message from an interconnect which is connected to the requesting processing unit. The response is detected by system logic and forwarded from the system logic to the requesting processing unit. The specific cache then sources the value to an interconnect which is connected to the requesting processing unit. The system memory detects the message and would normally source the value, but the response informs the memory device that the value is to be sourced by the cache instead. Since the cache latency can be much less than the memory latency, the read performance can be substantially improved with this new protocol.

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