Shared cache memory replacement control method and apparatus

Details Shared cache memory replacement control method and apparatus Shared cache memory replacement control method and apparatus

2005-04-05

2005-04-05

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S120000, C711S124000, C711S128000, C711S133000, C711S134000, C711S141000, C711S144000, C710S001000, C710S036000, C710S039000, C710S052000, C710S100000, C710S107000, C710S200000

Reexamination Certificate

active

06877067

ABSTRACT:
In a multiprocessor system in which a plurality of processors share an n-way set-associative cache memory, a plurality of ways of the cache memory are divided into groups, one group for each processor. When a miss-hit occurs in the cache memory, one way is selected for replacement from the ways belonging to the group corresponding to the processor that made a memory access but caused the miss-hit. When there is an off-line processor, the ways belonging to that processor are re-distributed to the group corresponding to an on-line processor to allow the on-line processor to use those ways.

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Albonesi, Nov. 16-18, 1999, IEEE, pp. 248-259.

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