Stacked card address assignment
Stacked I/O bridge circuit assemblies having flexibly...
Stacked semiconductor memory device with compound read buffer
Staggered polling of buffer descriptors in a buffer...
Staging buffer for translating clock domains when source...
Standalone storage system with multiple heads in an...
Standard ATA queuing automation in serial ATA interface for...
Standard channel I/O processor (SCIOP)
Standard configurable universal serial bus (USB) device...
Starvation avoidance mechanism for an I/O node of a computer...
State activated one shot with extended pulse timing for...
State indicating information setting circuit and status bit...
State machine and communication terminal
State machine based bus cycle completion checking in a bus bridg
State machine bus controller providing function and timing param
State machine design for generating half-full and half-empty fla
State machine for selectively performing an operation on a singl
State machine for selectively performing an operation on a...
State negotiation method in PCI-E architecture
Statistic method for arbitration