State machine bus controller providing function and timing param

Details State machine bus controller providing function and timing param State machine bus controller providing function and timing param

1997-06-16

1999-08-31

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Peripheral configuration

710 58, G06F 1314

Patent

active

059447990

ABSTRACT:
A state machine bus controller for interfacing the CPU of a micro-computer based system with memory and I/O device is described. The controller, while capable of interfacing with a bus which is synchronous in nature, can maintain synchronous handshake with more than one type of microprocessor while providing function and timing parameters to satisfy requirements of an asynchronous bus and more than one type of device which reside on the bus.

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